A Raspberry Pi controlling neuromorphic hardware

This thesis describes the integration of a Raspberry Pi, a credit-card-sized single board computer, into the Wafer Scale Integration (WSI) System of the BrainScaleS project. The Raspberry Pi’s task is to bundle all the interfaces necessary to manage the system’s elaborate power supply into one single-access, easy-to-use interface. To this purpose the Raspberry Pi replaced the former evaluation board responsible for power management, taking over all of its tasks and in addition providing faster and cheaper hardware. The integration took place in two main steps: configuring the Raspberry Pi’s hardware and adapting the control programme from the former board to the new hardware. The results of this thesis are the successful integration of the Raspberry Pi into the WSI system, which was proven by several communication tests between the Raspberry Pi and the rest of the system, and an easy-to-follow step-by-step guide on how to set up Raspberry Pis to manage additional systems

Electrical Characterisation of III-V Nanowire MOSFETs

The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to theoxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits

Low-Frequency Noise in TFETs

Nanowire tunnel field-effect transistors (TFETs) were investigated by carrying out noise measurements and low-temperature DC measurements. The TFET tunnelling junction was realised by a GaSb/InAs heterojunction resulting in a broken band gap. TFET noise currents were measured at frequencies between 10 Hz and 1 kHz. The results imply that noise in TFETs at the current state of development is dominated by generation-recombination processes caused by traps in the gate oxide. Trap densities between 10^20 cm^-3 eV^-1 and 10^22 cm^-3 eV^-1 were extracted from the noise measurements. The temperature-dependent DC measurements show that the TFETs' off-current is sensitive to the temperature, with lower off-currents at lower temperatures. This indicates that it is not only the tunnelling junction which is governing the off-current. It is concluded that in the devices' off-state electrons can still tunnel into the channel area through the broken band gap but require additional thermionic excitation over the bent channel conduction band to constitute a current.The ever-growing demand for electronic devices in all areas of our lives can only be satisfied due to the constant development of today’s most essential of all active electronic devices – the metal-oxide-semiconductor field-effect transistor (MOSFET). However, its further development is drawing to an end, so coming up with alternatives is of utmost importance. One of the most promising ones is the tunnel field-effect transistor (TFET). A MOSFET basically is an electrical switch. The current between two of the device’s contacts – source and drain – can be controlled by a third contact, the gate. In digital applications, such as all our computers and smartphones, MOSFETs only switch between an on- and an off-state, meaning flowing current or almost no current, respectively. The ability to switch between these two states as fast as possible is what governs a MOSFET’s speed and energy-efficiency. Over the last 50 years MOSFETs have undergone constant development to increase these measures. Due to the underlying physical principles that MOSFETs are based on, this development is drawing to an end. In a MOSFET electrons have to overcome an energy barrier to establish a current. With the gate contact this barrier can be raised (off-state) or lowered (on-state). This principle establishing the current is at the same time the principle which limits further scaling of MOSFETs as there are always a few electrons which can overcome the barrier – even in the device’s off-state. The idea for TFETs to overcome this limit is to control the current by opening or closing a narrow gap in the energy structure of the device. Instead of overcoming a barrier the electrons have to tunnel through it. In contrast to the MOSFET structure the electrons on the source side of the TFET structure face a restriction from the top which reduces the off-current. In my thesis I contribute to the development of TFETs as successors of or complements to MOSFETs by examining electrical noise and the current temperature dependence in TFETs. A well-known form of electrical noise is noise which finds its way into an audio signal (e. g. buzzing speakers). However, noise is present in all electrical signals and examining the noise in TFETs gives information about which parts of the devices require particular improvement to finally lead to industrially applicable TFETs benefitting the broad public

Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si

We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb tunneling field-effect transistors integrated on Si substrates. The best subthreshold swing, 68 mV/decade at VDS=0.3 V, was achieved for a device with 20-nm InAs diamter. The on-current for the same device was 35 µA/µm at VGS=0.5 V and VDS=0.5 V. The fabrication technique used allows downscaling of the InAs diameter down to 11 nm with a flexible gate placement

Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance.

Thin vertical nanowires based on III-V compound semiconductors are viable candidates as channel material in metal oxide semiconductor field effect transistors (MOSFETs) due to attractive carrier transport properties. However, for improved performance in terms of current density as well as contact resistance, adequate characterization techniques for resolving doping distribution within thin vertical nanowires are required. We present a novel method of axially probing the doping profile by systematically changing the gate position, at a constant gate length L g of 50 nm and a channel diameter of 12 nm, along a vertical nanowire MOSFET and utilizing the variations in threshold voltage V T shift (∼100 mV). The method is further validated using the well-established technique of electron holography to verify the presence of the doping profile. Combined, device and material characterizations allow us to in-depth study the origin of the threshold voltage variability typically present for metal organic chemical vapor deposition (MOCVD)-grown III-V nanowire devices

Thin-film design of amorphous hafnium oxide nanocomposites enabling strong interfacial resistive switching uniformity

A design concept of phase-separated amorphous nanocomposite thin films is presented that realizes interfacial resistive switching (RS) in hafnium oxide-based devices. The films are formed by incorporating an average of 7% Ba into hafnium oxide during pulsed laser deposition at temperatures ≤400°C. The added Ba prevents the films from crystallizing and leads to ∼20-nm-thin films consisting of an amorphous HfOx host matrix interspersed with ∼2-nm-wide, ∼5-to-10-nm-pitch Ba-rich amorphous nanocolumns penetrating approximately two-thirds through the films. This restricts the RS to an interfacial Schottky-like energy barrier whose magnitude is tuned by ionic migration under an applied electric field. Resulting devices achieve stable cycle-to-cycle, device-to-device, and sample-to-sample reproducibility with a measured switching endurance of ≥104 cycles for a memory window ≥10 at switching voltages of ±2 V. Each device can be set to multiple intermediate resistance states, which enables synaptic spike-timing-dependent plasticity. The presented concept unlocks additional design variables for RS devices

Ferroelectricity and negative piezoelectric coefficient in orthorhombic phase pure ZrO2 thin films

A new approach for epitaxial stabilisation of ferroelectric orthorhombic (o-) ZrO2 films with negative piezoelectric coefficient in ∼ 8nm thick films grown by ion-beam sputtering is demonstrated. Films on (011)-Nb:SrTiO3 gave the oriented o-phase, as confirmed by transmission electron microscopy and electron backscatter diffraction mapping, grazing incidence x-ray diffraction and Raman spectroscopy. Scanning probe microscopy techniques and macroscopic polarization-electric field hysteresis loops show ferroelectric behavior, with saturation polarization of ∼14.3 µC/cm2, remnant polarization of ∼9.3 µC/cm2 and coercive field ∼1.2 MV/cm. In contrast to the o-films grown on (011)-Nb:SrTiO3, films grown on (001)-Nb:SrTiO3 showed mixed monoclinic (m-) and o-phases causing an inferior remnant polarization of ∼4.8 µC/cm2, over 50% lower than the one observed for the film grown on (011)-Nb:SrTiO3. Density functional theory (DFT) calculations of the SrTiO3/ZrO2 interfaces support the experimental findings of a stable polar o-phase for growth on (011) Nb:SrTiO3, and they also explain the negative piezoelectric coefficient.This work was supported by: (i) the Portuguese Foundation for Science and Technology (FCT) in the framework of the Strategic Funding Contract UIDB/04650/2020 and (ii) Project NECL - NORTE-01-0145-FEDER-022096 and Project UID/NAN/50024/2019. This work has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 958174 (M-ERA-NET3/0003/2021 - NanOx4EStor). This work was also developed within the scope of the project CICECO-Aveiro Institute of Materials, UIDB/50011/2020 & UIDP/50011/2020, financed by national funds through the Portuguese Foundation for Science and Technology/MCTES. It is also funded by national funds (OE), through FCT – Fundação para a Ciência e a Tecnologia, I.P., in the scope of the framework contract foreseen in the numbers 4, 5 and 6 of the article 23, of the Decree-Law 57/2016, of August 29, changed by Law 57/2017, of July 19.The calculations were carried out at the OBLIVION Supercomputer (based at the High Performance Computing Center - University of Évora) funded by the ENGAGE SKA Research Infrastructure (reference POCI-01-0145-FEDER-022217 - COMPETE 2020 and the Foundation for Science and Technology, Portugal) and by the BigData@UE project (reference ALT20-03-0246-FEDER-000033 - FEDER and the Alentejo 2020 Regional Operational Program). Oblivion resources were accessed through the advanced computing projects CPCA/A2/5649/2020 and CPCA/A2/4628/2020, funded by FCT I.P. The authors gratefully acknowledge the HPC RIVR consortium (www.hpc-rivr.si) and EuroHPC JU (eurohpc-ju.europa.eu) for funding this research by providing computing resources of the HPC system Vega at the Institute of Information Science (www.izum.si)The calculations were carried out at the OBLIVION Supercomputer (based at the High Performance Computing Center - University of Évora) funded by the ENGAGE SKA Research Infrastructure (reference POCI-01-0145-FEDER-022217 - COMPETE 2020 and the Foundation for Science and Technology, Portugal) and by the BigData@UE project (reference ALT20-03-0246-FEDER-000033 - FEDER and the Alentejo 2020 Regional Operational Program). Oblivion resources were accessed through the advanced computing projects CPCA/A2/5649/2020 and CPCA/A2/4628/2020, funded by FCT I.P. The authors gratefully acknowledge the HPC RIVR consortium (www.hpc-rivr.si) and EuroHPC JU (eurohpc-ju.europa.eu) for funding this research by providing computing resources of the HPC system Vega at the Institute of Information Science (www.izum.si

Multi-level resistive switching in hafnium-oxide-based devices for neuromorphic computing

Abstract In the growing area of neuromorphic and in-memory computing, there are multiple reviews available. Most of them cover a broad range of topics, which naturally comes at the cost of details in specific areas. Here, we address the specific area of multi-level resistive switching in hafnium-oxide-based devices for neuromorphic applications and summarize the progress of the most recent years. While the general approach of resistive switching based on hafnium oxide thin films has been very busy over the last decade or so, the development of hafnium oxide with a continuous range of programmable states per device is still at a very early stage and demonstrations are mostly at the level of individual devices with limited data provided. On the other hand, it is positive that there are a few demonstrations of full network implementations. We summarize the general status of the field, point out open questions, and provide recommendations for future work

Multi-level resistive switching in hafnium-oxide-based devices for neuromorphic computing

Acknowledgements: Not applicable.In the growing area of neuromorphic and in-memory computing, there are multiple reviews available. Most of them cover a broad range of topics, which naturally comes at the cost of details in specific areas. Here, we address the specific area of multi-level resistive switching in hafnium-oxide-based devices for neuromorphic applications and summarize the progress of the most recent years. While the general approach of resistive switching based on hafnium oxide thin films has been very busy over the last decade or so, the development of hafnium oxide with a continuous range of programmable states per device is still at a very early stage and demonstrations are mostly at the level of individual devices with limited data provided. On the other hand, it is positive that there are a few demonstrations of full network implementations. We summarize the general status of the field, point out open questions, and provide recommendations for future work